View LC72342G_221663.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

Ordering number : EN*5799
CMOS IC
LC72341G/W, LC72342G/W, LC72343G/W
Low-Voltage Single-Chip Microcontrollers with OnChip PLL and LCD Driver Circuits
Preliminary Overview
The LC72341G/W, LC72342G/W, and LC72343G/W are single-chip microcontrollers with both a 1/4-duty 1/2-bias LCD driver circuit and a PLL circuit that can operate at up to 250 MHz integrated on the same chip. These ICs are ideal for use in portable audio equipment. Reference frequencies of 1, 3, 5, 6.25, 12.5, and 25 kHz can be provided. * Input frequency range -- FM band: 10 to 130 MHz 130 to 250 MHz -- AM band: 0.5 to 15 MHz
Functions
* High-speed programmable divider * Program memory (ROM) -- LC72341G/W: 2048 words x 16 bits (4KB) -- LC72342G/W: 3072 words x 16 bits (6KB) -- LC72343G/W: 4096 words x 16 bits (8KB) * Data memory (RAM) -- LC72341G/W: 128 words x 4 bits -- LC72342G/W: 192 words x 4 bits -- LC72343G/W: 256 words x 4 bits * Instruction cycle time -- 40 s (for all single-word instructions.) * Stack -- 4 levels (LC72341G/W) -- 8 levels (LC72342G/W, and LC72343G/W) * LCD driver -- 48 to 80 segments (1/4-duty 1/2-bias drive) * Timer interrupts -- One timer circuit providing intervals of 1, 5, 10, and 50 ms. * External interrupts -- One external interrupt (INT) * A/D converter -- Two channels (5-bit successive approximation) * Input ports -- 7 (Of which two can be switched to function as A/D converter inputs) * Output ports -- 6 (Of which one can be switched to function as the BEEP tone output. Two ports are open-drain ports.) * I/O ports -- 16 (Of which 8 can be selected to function as LCD ports as mask options.) * PLL circuit -- Two types of dead band control are supported, and an unlock detection circuit is included.
Package Dimensions
unit: mm 3159-QFP64G
[LC72341G, 72342G, 72343G]
SANYO: QFP64G
unit: mm 3159-SQFP64
[LC72341W, 72342W, 72343W]
SANYO: SQFP64
SANYO Electric Co.,Ltd. Semiconductor Bussiness Headquarters
TOKYO OFFICE Tokyo Bldg., 1-10, 1 Chome, Ueno, Taito-ku, TOKYO, 110-8534 JAPAN
31398RM (OT) No. 5799-1/12
LC72341G/W, 72342G/W, 72343G/W * IF counter -- HCTR input pin; 0.4 to 12 MHz * Voltage detection circuit (VSENSE) -- Detects the VDD voltage and sets a flag * External reset pin -- Restarts execution from location 0 when the CPU and PLL circuits are operating * Power on reset circuit -- Starts execution from location 0 at power on. * Universal counter -- 20 bits * Beep tones -- 3.1 and 1.5 kHz * Halt mode: The microcontroller operating clock is stopped * Backup mode: The crystal oscillator is stopped * An amplifier for a low-pass filter is built in * CPU and PLL circuit operating voltage -- 1.8 to 3.6 V * RAM data retention voltage -- 1.0 V or higher * Packages -- QIP-64G : 0.8-mm lead pitch -- SQFP-64 : 0.5-mm lead pitch Pin Assignment
* PE0 and PE1 are open-drain outputs. * The I/O ports can be set to input or output individually. * The functions of the segment/general-purpose ports can be set in bit units.
No. 5799-2/12
LC72341G/W, 72342G/W, 72343G/W Block Diagram
Divider System clock generator
Reference divider
Phasedetector
Programmable divider
PLL data latch
PLL control
LCD Time base control Lach count end Port driver
Universal counter (20 bits)
Pon reset
Address decoder Bus driver
Data latch/ Bus driver
Bank
Data latch/ Bus driver
Bus control
Data latch/ Bus driver
Doubler Data latch/ Bus driver Address decoder JMP CAL Return interrupt reset Beep tone Stack Bank Instruction decoder circuit
Skip
Program counter Data latch/ Bus driver
Common driver
Latch A
Judge
Data latch/ Bus driver
Latch B
Timer 0
Data latch/ Bus driver
Data bus
No. 5799-3/12
LC72341G/W, 72342G/W, 72343G/W
Specifications
Absolute Maximum Ratings at Ta = 25C, VSS = 0 V
Parameter Maximum supply voltage Input voltage Output voltage Symbol VDD max VIN VOUT1 VOUT2 IOUT1 IOUT2 Output current IOUT3 IOUT4 IOUT5 Allowable power dissipation Operating temperature Storage temperature Pd max Topr Tstg All input pins AOUT, PE All output pins except VOUT1 PC, PD, PG, PH, EO PB AOUT, PE S1 to S20 COM1 to COM4 Ta = -20 to +70C Conditions Ratings -0.3 to +4.0 -0.3 to VDD + 0.3 -0.3 to +15 -0.3 to VDD to + 0.3 0 to 3 0 to 1 0 to 2 300 3 300 -20 to +70 -45 to +125 Unit V V V V mA mA mA A mA mW C C
Allowable Operating Ranges at Ta = -20 to 70C, VDD = 1.8 to 3.6 V
Parameter Symbol VDD1 VDD2 VIH1 Input high-level voltage VIH2 VIH3 VIL1 Input low-level voltage VIL2 VIL3 VIN1 Input amplitude VIN2 VIN3 VIN4 Input voltage range VIN5 FIN1 FIN2 Input frequency FIN3 FIN4 FIN5 FIN6 Conditions CPU and PLL operating voltage Memory retention voltage VIH2, VIH3, AMIN, FMIN, Input ports except HCTR and XIN. RES Port PF VIL2, VIL3, AMIN, FMIN, Input ports except HCTR and XIN. RES Port PF XIN FMIN, AMIN FMIN HCTR ADI0, ADI1 XIN : CI 35 k FMIN : VIN2, VDD1 FMIN : VIN3, VDD1 AMIN (H) : VIN2, VDD1 AMIN (L) : VIN2, VDD1 HCTR : VIN4, VDD1 Ratings min 1.8 1.0 0.7 VDD 0.8 VDD 0.6 VDD 0 0 0 0.5 0.035 0.05 0.035 0 70 10 130 2 0.5 0.4 75 VDD VDD VDD 0.3 VDD 0.2 VDD 0.2 VDD 0.6 0.35 0.35 0.35 VDD 80 130 250 40 10 12 typ 3.0 max 3.6 Unit V V V V V V V V Vrms Vrms Vrms Vrms V kHz MHz MHz MHz MHz MHz
Supply voltage
Electrical Characteristics at Ta = -20 to 70C, VDD = 1.8 to 3.6 V (in the allowable operating ranges)
Parameter Symbol IIH1 Input high-level current IIH2 IIH3 IIL1 Input low-level current IIL2 IIL3 Input floating voltage Pull-down resistance Hysteresis Voltage doubler reference voltage Voltage doubler step-up voltage VIF RPD1 VH DBR4 Conditions XIN : VI = VDD = 3.0 V FMIN, AMIN, HCTR : VI = VDD = 3.0 V Ports PA/PF (with no pull-down resistor), PC, PD, PG, and PH. RES: VI = VDD = 3.0 V XIN : VI = VDD = VSS FMIN, AMIN, HCTR : VI = VDD = VSS Ports PA/PF (with no pull-down resistor), PC, PD, PG, and PH. RES: VI = VDD = VSS PA/PF with pull-down resistors used PA/PF with pull-down resistors used, VDD = 3 V RES Ta = 25C, referenced to VDD, C3 = 0.47 F 75 0.1 VDD 1.3 2.7 100 0.2 VDD 1.5 3.0 1.7 3.3 -3 -8 3 8 Ratings min typ max 3 20 3 -3 -20 -3 0.05 VDD 200 Unit A A A A A A V k V V V
DBR1, 2, 3 Ta = 25C, C1 = 0.45 F, C2 = 0.47 F, no load
No. 5799-4/12
LC72341G/W, 72342G/W, 72343G/W
Note: C1, C2, and C3 must be provided even if no LCD is used.
Electrical Characteristics at Ta = -30 to 70C, VDD = 1.8 to 3.6 V (in the allowable operating ranges)
Parameter Symbol VOH1 VOH2 VOH3 Output high-level voltage VOH4 VOH5 VOH6 VOL1 VOL2 VOL3 VOL4 Output low-level voltage VOL5 VOL6 VOL7 VOL8 Output off leakage current A/D conversion error IOFF1 IOFF2 PB : IO = -1 mA PC, PD, PG, PH : IO = -1 mA EO : IO = -500 A XOUT : IO = -200 A S1 to S20 : IO = -20 A: *1 COM1, COM2, COM3, COM4: IO = -100 A : *1 PB : IO = -50 A PC, PD, PE, PG, PH : IO = -1 mA EO : IO = -500 A XOUT : IO = -200 A S1 to S20 : IO = -20 A: *1 COM1, COM2, COM3, COM4 : IO = -100 A : *1 PE : IO = 5 mA AOUT : IO = 1 mA, AIN = 1.3 V, VDD = 3 V Ports PB, PC, PD, PG, PH, and EO Ports AOUT and PE ADI0, ADI1, VDD = VDD1 -3 -100 -1/2 Conditions Ratings min VDD - 0.7 VDD VDD - 0.3 VDD VDD - 0.3 VDD VDD - 0.3 VDD 2.0 2.0 0.7 VDD 0.3 VDD 0.3 VDD 0.3 VDD 1.0 1.0 1.0 0.5 +3 +100 +1/2 typ max Unit V V V V V V V V V V V V V V A nA LSB
Note: 1. Capacitors C1, C2, and C3 must be connected to the DBR pins.
Electrical Characteristics at Ta = -20 to 70C, VDD = 1.8 to 3.6 V (in the allowable operating ranges)
Parameter Falling supply voltage detection voltage Rising supply voltage detection voltage Pull-down resistance Symbol VSENSE1 VSENSE2 RPD2 IDD1 IDD2 Supply current IDD3 IDD4 Ta = 25C *2 Ta = 25C *2 TEST1, TEST2 VDD1 : FIN2 130 MHz, Ta = 25C VDD2: In halt mode at Ta = 25C, *3 VDD = 3.6 V, with the oscillator stopped, at Ta = 25C, *4 VDD = 1.8 V, with the oscillator stopped, at Ta = 25C, *4 Conditions Ratings min 1.6 VSENSE1 +0.1 10 10 0.1 1 0.5 typ 1.75 max 1.9 VSENSE1 +0.2 Unit V V k mA mA A A
Note: The halt mode current is measured with the CPU executing 20 instructions every 125 ms.
No. 5799-5/12
LC72341G/W, 72342G/W, 72343G/W
Note: 2. The VSENSE voltage When the VDD voltage falls, the VSENSE flag is set at the point that voltage falls under 1.75 V (typical). The TST instruction can be used to read the value of the VSENSE flag. Applications can easily determine when the batteries are exhausted by monitoring this flag. After VSENSE is set when the supply voltage falls, it will not be reset if the supply voltage rises by less than 0.1 V, because the voltages detected by the VSENSE circuit differ when the supply voltage is falling and when the supply voltage is rising.
When the Supply Voltage is Falling Note: 3. Halt Mode Current Test Circuit
When the Supply Voltage is Rising Note: 4. Backup Mode Current Test Circuit
All ports other than those specified in the figure must be left open. Set ports PC and PD to output. Select segments S13 to S20.
All ports other than those specified in the figure must be left open. Set ports PC and PD to output. Select segments S13 to S20.
No. 5799-6/12
LC72341G/W, 72342G/W, 72343G/W Pin Functions
Pin No. 64 1 63 2 Pin XIN XOUT TEST1 TEST2 I/O I O I I Function I/O circuit
Connections for a 75-kHz crystal oscillator element
IC test pins. These pins must be tied to ground. Input with built-in pulldown resistor
6 5 4 3
PA0 PA1 PA2 PA3 I
Special-purpose key return signal input ports designed with a low threshold voltage. When used in conjunction with port PB to form a key matrix, up to 3 simultaneous key presses can be detected. The four pull-down resistors are selected together in a single operation using the IOS instruction (PWn = 2, b1); they cannot be specified individually. Input is disabled in backup mode, and the pull-down resistors are disabled after a reset.
10 9 8 7
PB3 PB2 PB1 PB0 O
Special-purpose key source signal output ports. Since unbalanced CMOS output transistor circuits are used, diodes to prevent short-circuits when multiple keys are pressed are not required. These ports go to the output high-impedance state in backup mode. These ports go to the output high-impedance state after a reset and remain in that state until an output instruction (OUT, SPB, or RPB) is executed. Care is required in designing the output loads if these pins are used for functions other than key source outputs.
Unbalanced CMOS push-pull circuit
14 13 12 11 18 17 16 15
PC0 PC1 PC2 PC3 INT/PD0 PD1 PD2 PD3 General-purpose output ports with shared beep tone output function (PE0 only). The BEEP instruction is used to switch PE0 between the general-purpose output port and beep tone output functions. To use PE0 as a general-purpose output port, execute a BEEP instruction with b2 set to 0. Set b2 to 1 to use PE0 as the beep tone output port. The b0 and b1 bits are used to select the beep tone frequency. There are two beep tone frequencies supported. I/O General-purpose I/O ports*. PD0 can be used as an external interrupt port. Input or output mode can be set in a bit unit using the IOS instruction (Pwn = 4, 5). A value of 0 specifies input, and 1 specifies output. These ports go to the input disabled highimpedance state in backup mode. They are set to function as general-purpose input ports after a reset.
CMOS push-pull circuit
N-channel open drain
20 19
BEEP/PE0 PE1
When PE0 is set up as the beep tone output, executing an output instruction to PN0 only changes the state of the internal output latch, it does not affect the beep tone output in any way. Only the PE0 pin can be switched between the general-purpose output function and the beep tone output function; the PE1 pin only functions as a generalpurpose output. These pins go to the high-impedance state in backup mode and remain in that state until an output instruction or a BEEP instruction is executed. Since these ports are open-drain ports, resistors must be inserted between these pins and VDD. These ports are set to their general-purpose output port function after a reset. General-purpose input and A/D converter input shared function ports (PF2 is a generalpurpose input only port). The IOS instruction (Pwn = FH) is used to switch between the general-purpose input and A/D converter port functions. The general-purpose input and A/D converter port functions can be switched in a bit unit, with 0 specifying generalpurpose input, and 1 specifying the A/D converter input function. To select the A/D converter function, set up the A/D converter pin with an IOS instruction with Pwn set to 1. The A/D converter is started with the UCC instruction (b3 = 1, b2 = 1). The ADCE flag is set when the conversion completes. The INR instruction is used to read in the data. If an input instruction is executed for one of these pins which is set up for analog input, the read in data will be at the low level since CMOS input is disabled. In backup mode these pins go to the input disabled high-impedance state. These ports are set to their general-purpose input port function after a reset. The A/D converter is a 5-bit successive approximation type converter, and features a conversion time of 1.28 ms. Note that the full-scale A/D converter voltage (1FH) is (63 * 96)VDD. CMOS input/analog input
23 22 21
PF0/ADI0 PF1/ADI1 PF2 I
Note: * Applications must establish the output data in advance with an OUT, SPB, or RPB instruction and then set the pin to output mode with an IOS instruction when using the I/O switchable ports as output pins.
Continued on next page. No. 5799-7/12
LC72341G/W, 72342G/W, 72343G/W
Continued from preceding page.
Pin No. Pin I/O Function LCD driver segment output and general-purpose I/O shared function ports. The IOS instruction is used for switching both between the segment output and general-purpose I/O functions and between input and output for the general-purpose I/O port function.* * When used as segment output ports The general-purpose I/O port function is selected with the IOS instruction (Pwn = 8). 25 26 27 28 PG3/S20 PG2/S19 PG1/S18 PG0/S17 I/O 29 30 31 32 PH3/S16 PH2/S15 PH1/S14 PH0/S13 b0 = S17 to 20/PG0 to 3 (0: Segment output, 1: PG0 to 3) The general-purpose I/O port function is selected with the IOS instruction (Pwn = 9). b0 = S13 to 16/PH0 to 3 (0: Segment output, 1: PH0 to 3) * When used as general-purpose I/O ports The IOS instruction (Pwn = 6,7) is used to select input or output. Note that the mode can be set in a bit unit. b0 = PG0 b1 = PG1 b2 = PG2 b3 = PG3 [0: Input, 1: Output] b0 = PH0 b1 = PH1 b2 = PH2 b3 = PH3 [0: Input, 1: Output] I/O circuit CMOS push-pull circuit
In backup mode, these pins go to the input disabled, high-impedance state if set up as general-purpose outputs, and are fixed at the low level if set up as segment outputs. These ports are set up as segment outputs after a reset. Although the general-purpose port/LCD port setting is a mask option, the IOS instruction must be used as described above to set up the port function.
LCD driver segment output pins. A 1/4-duty 1/2-bias drive technique is used. S16 to S1 33 to 44 O The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level.
CMOS push-pull circuit
COM4 COM3 COM2 COM1
45 46 47 48 O
LCD driver common output pins. A 1/4-duty 1/2-bias drive technique is used. The frame frequency is 75 Hz. In backup mode, the outputs are fixed at the low level. After a reset, the outputs are fixed at the low level.
DBR4 DBR3 DBR2 DBR1
49 50 51 52 LCD power supply stepped-up voltage pins.
System reset input. 53 RES I In CPU operating mode or halt mode, applications must apply a low level for at least one full machine cycle to reset the system and restart execution with the PC set to location 0. This pin is connected in parallel with the internal power on reset circuit. Universal counter dedicated input port. * When taking frequency measurements, select the HCTR frequency measurement mode and measurement time with the UCS instruction (b3 = 0, b2 = 0) and start the count with a UCCinstruction. UCS 70 HCTR I b3, 0 0 1 1 b2 0 1 0 1 Input pin HCTR -- -- -- Measurement mode Frequency measurement UCS b1, 0 0 1 1 b0 0 1 0 1 Measurement time 1 ms 4 ms 8 ms 32 ms
CMOS input/analog input
The CNTEND flag is set when the count completes. Since this circuit functions as an AC amplifier, always use capacitor coupling with the input signal. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. Note: * Applications must establish the output data in advance with an OUT, SPB, or RPB instruction and then set the pin to output mode with an IOS instruction when using the I/O switchable ports as output pins.
Continued on next page. No. 5799-8/12
LC72341G/W, 72342G/W, 72343G/W
Continued from preceding page.
Pin No. Pin I/O Function I/O circuit CMOS amplifier input FM VCO (local oscillator) input. 56 FMIN I This pin is selected with the PLL instruction CW1. The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode.
AM VCO (local oscillator) input. This pin and the bandwidth are selected with the PLL instruction CW1. CW1 57 AMIN I b1, 1 1 b0 0 1 Bandwidth 2 to 40 MHz (SW) 0.5 to 10 MHz (MW, LW) CMOS amplifier input
The input must be capacitor coupled. Input is disabled in backup mode, in halt mode, after a reset, and in PLL stop mode. Push-pull CMOS output
59
E0
O
The main charge pump output. When the local oscillator frequency divided by N is higher than the reference frequency a high level is output, when lower, a low level is output, and the pin is set to the high-impedance state when the frequencies match. Output goes to the high-impedance state in backup mode, in halt mode, after a reset, and in PLL stop mode.
60 61 62
AIN AOUT AGND O
Transistor used for the low-pass filter amplifier. Connect AGND to ground.
24 58 55
VSS VSS VDD
-- -- --
Power supply pin. This pin must be connected to ground. Power supply pin. This pin must be connected to ground. Power supply pin. This pin must be connected to VDD.
Handling of Unused Pins
Pin No. Pin 3 to 6 PA port 7 to 10 PB port 11 to 14 PC port 15 to 18 PD port 19, 20 PE port 21 to 23 PF port 25 to 28 PG/S ports 29 to 32 PH/S ports 33 to 41 S port 45 to 48 COM 49 DBR1 50 DBR2 51 DBR3 52 DBR4 53 RES 54 HCTR 56 FMIN 57 AMIN 59 EO 60 AIN 61 AOUT 63 TEST1 2 TEST2 I/O type I O I/O I/O O I I/O/S I/O/S O O -- -- -- -- I I I I O I O I I Pin handling Connect to VDD or VSS. May be left open if the pull-up resistor is selected with the IOS instruction. Open Connect to VDD or VSS when input is selected. Leave open if output is selected. Connect to VDD or VSS when input is selected. Leave open if output is selected. Open Connect to VDD or VSS. The PF2 pin only may be left open if the pull-up resistor is selected with the IOS instruction. Connect to VDD or VSS when input is selected. Leave open if output or LCD operation is selected. Connect to VDD or VSS when input is selected. Leave open if output or LCD operation is selected. Open Open Connect to DBR2 through a capacitor. Connect to DBR1 through a capacitor. Connect to VSS through a capacitor. Connect to VSS through a capacitor. VDD VSS Leave open if FMIN is used. VSS VSS Open VSS Open Connect to VSS or leave open. Connection to VSS is preferable. Connect to VSS or leave open. Connection to VSS is preferable.
No. 5799-9/12
LC72341G/W, 72342G/W, 72343G/W Mask Options
Port 1 2 3 4 5 6 7 8 PG3/S20 PG2/S19 PG1/S18 PG0/S17 PH3/S16 PH2/S15 PH1/S14 PH0/S13 Selection General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port General-purpose port LCD port LCD port LCD port LCD port LCD port LCD port LCD port LCD port
Development Environment and Tools * The LC72P341 is available as a OTP version. * The LC72EV340 is available as an evaluation chip. * A total debugging system is formed by the combination of the TB-72EV32 evaluation chip board, the RE32 multifunction emulator, and a personal computer for system control.
No. 5799-10/12
LC72341G/W, 72342G/W, 72343G/W Instruction Set
Instruction group Mnemonic AD Addition instructions ADS AC ACS AI AIS AIC AICS SU Subtraction instructions SUS SB SBS SI SIS SIB SIBS SEQ Comparison instructions SEQI SNEI SGE SGEI SLEI ANDI Logic and arithmetic instructions ORI EXLI AND OR EXL SHR Transfer instructions LD ST MVRD MVRS MVSR MVI TMT TMF JMP CAL RT RTI SS RS TST TSF TUL I I I I N N N N N Opcode 1st r r r r M M M M r r r r M M M M r M M r M M M M M r r r r r M r M M1 M M M ADDR ADDR M r M r M2 I N N 2nd M M M M I I I I M M M M I I I I M I I M I I I I I M M M 15 Machine code 12 11 00 01 10 11 00 01 10 11 00 01 10 11 00 01 10 11 00 10 01 10 11 11 01 11 10 00 10 00 00 00 01 10 11 00 01 00 01 8 DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH DH 00 DH DH DH DH DH DH DH DH 7 DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL DL 1110 DL DL DL DL DL1 DL DL DL 43 r r r r I I I I r r r r I I I I r I I r I I I I I r r r r r r r r DL2 I N N 0 r (r) + (M) r (r) + (M), skip if carry r (r) + (M) + C r (r) + (M) + C, skip if carry M (M) + I M (M) + I, skip if carry M (M) + I + C M (M) + I + C, skip if carry r (r) - (M) r (r) - (M), skip if borrow r (r) - (M) - b r (r) - (M) - b, skip if borrow M (M) - I M (M) - I, skip if borrow M (M) - I - b M (M) - I - b, skip if borrow (r) (M), skip if zero (M) -- I, skip if zero (M) -- I, skip if not zero (r) -- (M), skip if not borrow (M) -- I, skip if not borrow (M) -- I, skip if borrow M (M) AND I M (M) OR I M (M) XOR I r (r) AND M r (r) OR M r (r) XOR M Shift r right with carry r (M) M (r) [DH, rn] (M) M [DH, rn] [DH, DL1] [DH, DL2] MI if M (N) = all 1, then skip if M (N) = all 0, then skip PC ADDR PC ADDR, Stack (PC) + 1 PC Stack PC Stack, BANK Stak, carry stack N N N N N (Status reg. I)N 1 (Status reg. I)N 0 if (Status reg. I)N = all 1, then skip if (Status reg. I)N = all 0, then skip if Unlock F/F (N) = all 0, then skip Continued on next page. Operation
0100 0100 0100 0100 0101 0101 0101 0101 0110 0110 0110 0110 0111 0111 0111 0111 0001 0001 0000 0001 0001 0000 0010 0010 0011 0010 0010 0011 0000 1101 1101 1101 1101 1110 1110 1111 1111 100 101 0000 0000 1111 1111 1111 1111 0000
Memory test instructions Jump and subroutine call instructions
ADDR (13 bits) ADDR (13 bits) 0000 0000 1111 1111 1111 1111 0000 1000 1001 000 I 001 I 01 I 10 I 1101
Status register test and flip-flop control instructions
No. 5799-11/12
LC72341G, W, LC72342G, W, LC72343G, W
Continued from preceding page. Instruction group Peripheral hardware control instructions Mnemonic PLL TMS UCS UCC BEEP DZC BANK IOS INR I/O instructions IN OUT SPB RPB TPT TPF LCD control instructions LCDA LCDB LCPA LCPB HALT CKSTP NOP Opcode 1st M I I I I I I Pn M M M Pn Pn Pn Pn M M M M I I Rn Pn Ph N N N N I I I I 2nd r 15 Machine code 12 11 10 8 DH 7 DL 1100 0001 0010 0110 1011 0111 Pn DL DL DL Pn Pn Pn Pn DL DL DL DL 0100 0101 0000 43 r I I I I I I I r Pn Pn N N N N DIGIT DIGIT DIGIT DIGIT I LCD (DIGIT) Logic Array M HALT reg. I, then CPU Stop Stop Xtal OSC No operation 0 PLL reg. PLL data Timer reg. I UCS reg. I UCC reg. I BEEP reg. I DZC reg. I BANK I IOS reg. Pn I M (Rn reg.) M (Pn) Pn M (Pn) N 1 (Pn) N 0 if (Pn) N = all 1, then skip if (Pn) N = all 0, then skip LCD (DIGIT) M Operation
1111 0000 0000 0000 0000 0000 0000 1111 0011 1110 1110 0000 0000 1111 1111 1100 1100 1100 1100 0000 0000 0000
0000 0000 0000 0000 0000 0000 1110 10 10 11 DH DH DH
0010 0011 1100 1101 00 01 10 11 DH DH DH DH
Other instructions
0000 0000 0000
s No products described or contained herein are intended for use in surgical implants, life-support systems, aerospace equipment, nuclear power control systems, vehicles, disaster/crime-prevention equipment and the like, the failure of which may directly or indirectly cause injury, death or property loss. s Anyone purchasing any products described or contained herein for an above-mentioned use shall: Accept full responsibility and indemnify and defend SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors and all their officers and employees, jointly and severally, against any and all claims and litigation and all damages, cost and expenses associated with such use: Not impose any responsibility for any fault or negligence which may be cited in any such claim or litigation on SANYO ELECTRIC CO., LTD., its affiliates, subsidiaries and distributors or any of their officers and employees jointly or severally. s Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. SANYO believes information herein is accurate and reliable, but no guarantees are made or implied regarding its use or any infringements of intellectual property rights or other rights of third parties. This catalog provides information as of March, 1998. Specifications and information herein are subject to change without notice. PS No. 5799-12/12

▲Up To Search▲

Price & Availability of LC72342G

	To Download LC72342G Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .